I²C Slave Interface Specification
This document outlines the I²C command protocol for the WE2-based slave device, including packet structures, command/feature definitions, and waveform examples.
I²C Slave Address
The I²C slave device is identified by a 7-bit address. For this implementation, the slave address is configured as:
| Operation | 7-bit Address | R/W Bit | 8-bit Bus Address |
|---|---|---|---|
| Write | 0x62 |
0 |
0xC4 |
| Read | 0x62 |
1 |
0xC5 |
I²C Packet Format
The I2C protocol ensures data integrity and reliability using CRC. The payload size is limited to 256 bytes per packet. The device echoes the feature & command in the response to confirm reception.
I²C Write Packet Format
| Field | Size | Description |
|---|---|---|
saddr |
1 byte | Slave Address + W (0x62 << 1) |
featr |
1 byte | Feature, identifies the function block (e.g., OTA, Register) |
cmd |
1 byte | Specifies the command (e.g., start, write, erase, etc.). |
length |
2 bytes | Length of the following payload data |
payload |
0–256 bytes | Payload (register address/data, firmware chunks, etc.) |
crc |
2 bytes | CRC-16 (CCITT) over Feature byte to last data byte |
I²C Read Packet Format
The I²C read packet is preceded by an appropriate read command request (write packet).
| Field | Size | Description |
|---|---|---|
saddr |
1 byte | Slave Address + R (0x62 << 1) + 1 |
featr |
1 byte | Slave typically echos the feature from the request |
cmd |
1 byte | Slave typically echos the command from the request |
length |
2 bytes | Length of the payload response |
payload |
0–256 bytes | Response data (e.g., register values, status) |
crc |
2 bytes | CRC-16 (CCITT) over Feature byte to last data byte |
Feature and Command Codes
Feature Code Table
| Feature Enum | Code |
|---|---|
I2CCOMM_FEATURE_OTA_RESERVED |
0x50 |
I2CCOMM_FEATURE_OTA_ACCESS |
0x51 |
I2CCOMM_FEATURE_CTS_ACCESS |
0x80 |
I2CCOMM_FEATURE_REG_MEM_ACCESS |
0x8A |
Command Codes
FEATURE: CTS System Access Commands
| Command Enum | Value | Description | Payload Contents |
|---|---|---|---|
I2C_CMD_CTS_RESET |
0x01 |
CTS soft-reset | 0 bytes |
I2C_CMD_CTS_GET_STATUS |
0x02 |
Request the current I²C status | Req: 0 bytes Resp: 1 byte: status flags |
I2C_CMD_CTS_CV_RESET |
0x03 |
Reset the CV module | 0 bytes |
I2C_CMD_CTS_GET_STATUS will return a status byte with the bit masks shown below. The status byte is cleared after reading.
| Bit Position | Mask (hex) | Name | Meaning |
|---|---|---|---|
| 0 | 0x01 |
I2C_STATUS_BUSY |
Transaction in progress |
| 1 | 0x02 |
I2C_STATUS_CRC_ERR |
CRC/checksum failure |
| 2 | 0x04 |
I2C_STATUS_RX_ERR |
Read error (NACK, overrun, etc.) |
| 3 | 0x08 |
I2C_STATUS_MEM_ERR |
Memory/register address error |
| 4 | 0x10 |
I2C_STATUS_EEPROM_ERR |
EEPROM load/save failure |
| 5 | 0x20 |
I2C_STATUS_FEATURE_NOT_FOUND |
Unknown feature code |
| 6 | 0x40 |
I2C_STATUS_CMD_NOT_FOUND |
Unknown command for given feature |
| 7 | 0x80 |
I2C_STATUS_ERR |
General error |
FEATURE: Memory Access Commands
| Command Enum | Value | Description | Payload Contents |
|---|---|---|---|
I2C_CMD_MEM_READ |
0x01 |
Read N bytes from the given address | Req: 4 bytes: <addr_MSB, addr_LSB, len_MSB, len_LSB>Resp: N bytes: data at address |
I2C_CMD_MEM_WRITE |
0x02 |
Write N bytes to the given address | Req: 4+N bytes: <addr_MSB, addr_LSB, len_MSB, len_LSB, data[0..N-1]> |
For I2CCOMM_FEATURE_REG_MEM_ACCESS, the I2C_STATUS_MEM_ERR flag will be set if any of the following conditions occur:
-
A write is attempted to a read-only register.
-
The register address is not 4-byte aligned (i.e., not a multiple of 4).
-
The data payload size is not a multiple of 4 bytes, which is required to match the register word size.
FEATURE: OTA Access Commands
| Command Enum | Value | Description | Payload Contents |
|---|---|---|---|
I2CCOMM_CMD_OTA_JUMP2UPG |
0x08 |
Trigger a jump to the OTA firmware upgrade bootloader | 0 bytes |
I²C Example Waveforms
I²C read CTS status (Two-Part)
This example shows the master writing the status‐request packet (no payload) and then performing a repeated‐start read to obtain the 1-byte I²C status.
Step 1: Send command (Write Transaction)
| Field | Size | Description |
|---|---|---|
saddr |
1 byte | I²C Slave Address + Write bit (0xc4 = 7-bit addr 0x62, shifted + W) |
featr |
1 byte | Feature byte to identify module (e.g., 0x80 = CTS access) |
cmd |
1 byte | Command code (e.g., 0x02 = get status) |
length |
2 bytes | Payload length in bytes (0x0000 = 0 bytes) |
crc |
2 bytes | CRC-16-CCITT over featr to last payload byte |
Step 2: Get response (Read Transaction)
| Field | Size | Description |
|---|---|---|
saddr |
1 byte | I²C Slave Address + Read bit (0xc5 = 7-bit addr 0x62, shifted + R) |
featr |
1 byte | Slave echos feature byte |
cmd |
1 byte | Slave echos command code |
length |
2 bytes | Slave responsds with payload length |
payload |
1 byte | Slave responds with CTS status |
crc |
2 bytes | Slave responds with CRC-16-CCITT over featr to last payload byte |
I²C write of 32-bit data to a register
This example shows the I²C master writing 32-bit data to a register: 0x0050 = 0xdeadbeef.
Transaction Breakdown
| Field | Size | Description |
|---|---|---|
saddr |
1 byte | I²C Slave Address + Write bit (0xc4 = 7-bit addr 0x62, shifted + W) |
featr |
1 byte | Feature byte to identify module (e.g., 0x8A = register/memory block) |
cmd |
1 byte | Command code (e.g., 0x02 = memory write) |
length |
2 bytes | Payload length in bytes (0x0008 = 8 bytes total) |
payload |
8 bytes | Payload data: mem_addr=0x0050 (2 bytes), mem_size=0x0004 (2 bytes), followed by mem_data=0xdeadbeef (4 bytes in this example) |
crc |
2 bytes | CRC-16-CCITT over featr to last payload byte |
I²C read of 32-bit data from a register (Two-Part)
This example shows the I²C master reading 32-bit data from a register.
Step 1: Send Read Request Command (Write Transaction)
| Field | Size | Description |
|---|---|---|
saddr |
1 byte | I²C Slave Address + Write bit (0xc4 = 7-bit addr 0x62, shifted + W) |
featr |
1 byte | Feature byte to identify module (e.g., 0x8A = register/memory block) |
cmd |
1 byte | Command code (e.g., 0x01 = memory read) |
length |
2 bytes | Payload length in bytes (0x0004 = 4 bytes total) |
payload |
8 bytes | Payload data: mem_addr=0x0050 (2 bytes), mem_size=0x0004 (2 bytes) |
crc |
2 bytes | CRC-16-CCITT over featr to last payload byte |
Step 2: Get response (Read Transaction)
| Field | Size | Description |
|---|---|---|
saddr |
1 byte | I²C Slave Address + Read bit (0xc5 = 7-bit addr 0x62, shifted + R) |
featr |
1 byte | Slave echos feature byte |
cmd |
1 byte | Slave echos command code |
length |
2 bytes | Slave responds with payload length |
payload |
8 bytes | Slave responds with memory data: 0xdeadbeef (slave does not echo mem_addr/ mem_data) |
crc |
2 bytes | Slave responds with CRC-16-CCITT over featr to last payload byte |
This two-step process allows the master to request a specific register and then read the response with data integrity ensured via CRC.
CRC Specification
-
CRC Type: CRC-16-CCITT (Reflected)
-
Polynomial:
0x1021 - Initial Value:
0xFFFF - Input Reflection: True
- Output Reflection: True
- Final XOR Value:
0x0000 -
Computed Over: All bytes from
featurethrough the last byte of the payload -
Note: The slave address and I²C start/stop conditions are excluded
- CRC Output: Two bytes, sent LSB first (
crc[0],crc[1])